A variable delay circuit is a circuit capable of adjusting a delay amount between input and output of a signal. FIG. 8 is a view illustrating a configuration example of a conventional variable delay circuit. In the variable delay circuit illustrated in FIG. 8, plural unit delay circuits 100 are connected in series. Each of the unit delay circuits 100 includes inverters 101, 102, and a selector 103.
When a logical value of a delay set signal SDLY input thereto is “0” (zero), a signal input to a first input terminal is output from a first output terminal via the inverter 101, and a signal input to a second input terminal is output from a second output terminal via the selector 103 and the inverter 102 in the unit delay circuit 100. When the logical value of the delay set signal SDLY input thereto is “1”, the signal input to the first input terminal is output from the second output terminal via the inverter 101, the selector 103, and the inverter 102 in the unit delay circuit 100.
In the variable delay circuit illustrated in FIG. 8, an input signal SIN is input to a first input terminal of a first stage unit delay circuit 100, and an output signal SOUT is output from a second output terminal of the first stage unit delay circuit 100. Besides, a first output terminal of an i-th stage unit delay circuit 100 and a first input terminal of an (i+1)-th stage unit delay circuit 100 are connected, and a second input terminal of the i-th stage unit delay circuit 100 and a second output terminal of the (i+1)-th stage unit delay circuit 100 are connected. A delay set signal SDLY[i] is input to the i-th stage unit delay circuit 100. Here, “i” is a subscript, and “i” is a natural number satisfying “‘i’=1 to ‘n’”.
As stated above, the plural unit delay circuits 100 are connected in series, and the number of inverters between the input and output of the signal is controlled in accordance with the delay set signal SDLY[1:n], and thereby, it is possible for the variable delay circuit to adjust a delay amount between the input and output. Note that resolution of delay time at the variable delay circuit illustrated in FIG. 8 is determined by an intrinsic delay of the unit delay circuit 100.
When the signal is sped up while maintaining the number of delay stages in the variable delay circuit as illustrated in FIG. 8, it is preferably to have higher resolution of the delay time, namely, the delay time of the unit delay circuit is preferably to be short. For example, it is possible for the unit delay circuit 100 to shorten the delay time by making sizes of the inverters 101, 102 large, but a component area increases. Besides, the sizes of the inverters 101, 102 depend on a technology if they are tried to be made large, and there is a limit as device characteristics to shorten the delay time. It is conceivable to shorten the delay time by making the unit delay circuit 100 to have only one inverter either of the inverter 101 or the inverter 102, but the inverter exists at one side of either an input side or an output side, and a waveform deteriorates at the side where the inverters do not exist. The delay time changes caused by the deterioration of the waveform, and linearity of the delay time in accordance with the number of delay stages is lost in the variable delay circuit.
Besides, a technology is proposed in which resolution of delay time is set to be (t2−t1) by changing the number of buffers and selectors where an input signal is to be passed in a delay circuit including buffers each having a delay time t1 and selectors each having a delay time t2 (t1<t2<t1×2) (refer to Patent Document 1). A technology is proposed in which a first delay circuit where plural delay elements are connected in series and a delay time is adjusted by switching the number of delay elements where a signal is to be passed, and a second delay circuit including a delay element having a delay time which is not divided by the delay time at the delay element of the first delay circuit are combined to thereby improve resolution of the delay time compared to a case in which only the first delay circuit is included (refer to Patent Document 2). A technology is proposed in which logical inversion type two-input selectors are connected in multistage, an inversion signal of an input signal is input to an odd numbered selector, a non-inversion signal of the input signal is input to an even numbered selector, the number of stages of the selectors where the input signal is to be passed is switched to thereby adjust the delay time, and a duty ratio of the signal is maintained (refer to Patent Document 3).
[Patent Document 1] Japanese Laid-open Patent Publication No. 2005-50235
[Patent Document 2] Japanese Laid-open Patent Publication No. 2009-10737
[Patent Document 3] Japanese Laid-open Patent Publication No. 2001-282381